Published Articles
2003
Review of trench and via plasma etch issues for copper dual damascene in undoped and fluorine—doped silicate glass oxide, D.L. Keil, B.A. Helmer, and S. Lassig, Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, September
Abstract: Dual damascene dielectric etch technology is emerging as a key enabler for advanced integration schemes. Early implementations of copper dual damascene processes favored the trench—first approach. This approach has now been largely superseded by the via—first scheme for technology nodes below 250 nm. Several etch issues typically arise when implementing either of these approaches. The via—first approach can lead to either via veils or excessive faceting problems when the trench is etched. The traditional trench—first approach requires long via overetches and very high selectivity to the underlayer so that allowance can be made for vias that are misaligned or placed outside the trenches. Trench—first lithography employing organic resists often requires patterning over nonplanar surfaces, which can result in narrow process windows. Both the via—first and trench—first approaches increasingly require etching the trench without a stop layer. This places exacting demands on etch uniformity, etch front control, and sidewall profile angle control. Control of these issues is enhanced when the etch mechanisms responsible for driving them are understood. These and other issues as well as the current understanding of the relevant mechanisms are discussed for implementing copper dual damascene structures in plasma enhanced chemical vapor deposition undoped silicate glass or fluorinated silicate glass oxide films.
© 2003 American Vacuum Society
Integrating High—K Dielectrics: Etched Polysilicon or Metal Gates?, Tom Schram, Stephan Beckx, Stefan De Gendt, IMEC; Johan Vertommen, Steve Lee, Lam Research Corporation, Solid State Technology, June
Abstract: There is an immediate need for reduced gate leakage/higher capacitance gate stacks for stand—by low power applications. For high—performance applications, where leakage is less of a restraining factor, the motivation for the introduction of high k dielectrics predominantly comes from the manufacturability difficulties of sub—1.0nm SiO2—based dielectric layers. In response to these challenges, conventionally etched HfO2—based polysilicon and TaN—gated NMOS devices, featuring gate lengths down to 65nm, have been manufactured, and functional HfO2—based transistors, both with polysilicon and metal gate electrodes, have been demonstrated. The results showed the viability of etching high—k dielectric gate stacks in a single chamber using standard processing equipment.
2002
Integrating Dielectric Etching with 193nm Resists, Steve Lassig and Eric Hudson, Solid State Technology, October
Abstract: The introduction of 193nm lithography into 130nm production lines has improved lithographic capability, but has also created significant integration issues at the etch steps. The culprit is inferior etch resistance, reduced mechanical stability of printed features, and a reduction in thickness relative to 248nm resists. The industry is responding with new and novel integration schemes such as metal hardmasks, new etch chemistries, and pre—etch treatments.
Photoresist Trimming: Etch Solutions to CD Uniformity and Tuning, Shyam Ramalingam, Chris Lee, and Vahid Vahedi, Semiconductor International, September
Abstract: Photoresist trimming is designed to obtain acceptable feature profiles in sub—130nm linewidths. For logic applications, the process offers a means of shrinking gate length without using advanced lithography. This article explains how controlled and uniform trimming to sub—130nm linewidths was achieved on developed photoresist patterns with a Cl2/HBr/O2 plasma process in an inductively coupled plasma etch system.
Etching Sub—0.18 Micron Trenches, Roger Patrick et al, European Semiconductor, June
Abstract: Different devices have different requirements for shallow trench isolation (STI). Reported here is development work at STMicroelectronics where process parameters were varied and found to impact the different etch steps in a very predictable manner. Performing an in situ clean following every wafer pass provides a consistent process environment. Mixing STI etch with polysilicon or W6 gate etch recipes in the same chamber can significantly improve tool productivity.
Reprints Available
In Situ Processing for Dielectric Etch, Steve Lassig, Semiconductor Fabtech, 16th Edition (~May/June)
Abstract: In situ processing, where multiple operations are performed in a single chamber without interruption, is fast becoming an important industry trend for improving cost of ownership, productivity, and performance. Though the benefits are significant, the challenges and complexity of integrating multiple processes have slowed development until now. Technologies developed for dielectric and silicon etch at Lam enable this approach. In this paper, several key dielectric etch applications are discussed — including in situ etch processing for high—aspect—ratio contact and dual damascene — which are now in production.
Reprints Available
Investigating an Integrated Approach to Etch Emissions Management, Steve Whitten and Mat Waltrip, MICRO, March
Abstract: An exhaust management system developed to meet the industry's global warming perfluorocarbon (GWP) emissions targets provides cost and time savings and can lower 300mm tool footprint requirements below those of 200mm fabs.
Integration of Ultra Low K Dielectrics for CMP, S. Jew, S. Srivatsan, K.Y. Ramanujam, et al, European Semiconductor, March
Abstract: As they undergo the CMP process, the ultra low k materials of the future bring with them a greater risk of fracturing, cracking, and adhesive problems, due, in particular, to their increased porosity. Lam researchers discuss the integration of ultra low k for the 100nm generation.
Reprints Available
Selective Removal Strategies for Low K Dual Damascene, Steve Lassig, Simon McClatchie, and Adrian Kiermasz, Semiconductor Fabtech, 15th Edition (~January/February)
Abstract: While copper integration is fairly advanced, low k materials present a wide range of new integration challenges because of their lower density, inferior mechanical properties, and typically increased organic content. In dual damascene applications, they are layered between a variety of other films. The number of stack combinations and requirements necessitate developing processes and process systems that are highly flexible and provide large processing windows. This paper discusses challenges and strategies for selective removal processes and equipment for low k integration, including those for etching and chemical mechanical planarization (CMP).
Reprints Available
2001
CMP's "Center Spike": A Wafer Problem, Yehiel Gotkis, David Wei, John Boyd, and Rod Kistler, Solid State Technology, September
Direct CMP for STI Processing, Eugene Zhao and C. Shan Xu, Semiconductor International, June
Empirical—based Modeling for Control of CMP Removal Uniformity, Alan Jensen, Peter Renteln, and Stephen Jew, Lam; Chris Raeder and Patrick Cheung, Advanced Micro Devices Inc., Solid State Technology, June
Navigating Yield Through the Maze of Copper CMP Defects, Sumit Guha and Anantha Sethuraman, KLA—Tencor; Yehiel Gotkis and Rodney Kistler, Lam; and Scott Steckenrider, Cabot Corp., Solid State Technology, May
Reducing Risk at 300mm, David Hemker, Yield Management Solutions, April
Top Surface Imaging Improves Copper Process Resolution, Bill Gadson, Tactical Fabs Inc., and Steve Lassig, Nancy Tran, and Tom Ni, Lam, Solid State Technology, March
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